As an X-Y address type solid-state imaging device, for example, an MOS type solid-state imaging device, one configured by a large number of unit pixels, each unit pixel comprised of three transistors, arranged in a matrix has been known. The configuration of a unit pixel in this case is shown in FIG. 1. As clear from the figure, a unit pixel 100 has a photodiode (PD) 101, a transfer transistor 102, an amplifier transistor 103, and a reset transistor 104.
An MOS type solid-state imaging device employing the above pixel configuration operates to make the potential of a floating node N101 a low level (hereinafter described as an “L level”) through the reset transistor 104 from a drain line 105 during the period where a row is not selected and make the potential of the floating node N101 a high level (hereinafter, described as an “H level”) when the row is selected.
As explained above, a conventional MOS type solid-state imaging device configured by unit pixels, each comprising three transistors, arranged in a matrix makes the potential of the floating node N101 the L level (0V) during a nonselection period, therefore sometimes electrons leaked from the floating node N101 to the photodiode 101 and noise was generated due to this leakage.